1. Field of the Invention
This invention relates to a delay circuit which determines delay amount of pulse signals by changing the capacity and a semiconductor device which can be connected to other semiconductor devices containing different signal setup time and hold time by applying this delay circuit.
2. Description of Related Art
Any conventional semiconductor system like a digital integrated circuit incorporates a number of input/output terminals receiving and externally transmitting a variety of pulse signals and a clock terminal receiving external clock pulses. Conventionally, one kind of proper setup time and hold time are prescribed respectively for input terminals. The terms "setup time" and "hold time" respectively designate a kind of the timing condition when delivering an input signal to more than two kinds of input terminals of a semiconductor device.
Concretely, the term "setup time" designates such a specific moment at which a semiconductor device can correctly execute the prescribed operation in such a state where the signal condition of another input terminal is remained at a specific level a certain seconds before allowing an input signal (received by a terminal like a clock input terminal for example) to vary itself. On the other hand, the term "hold time" designates such a specific moment at which a semiconductor device can correctly execute the prescribed operation in such a state where the signal condition of another input terminal is remained at a specific level a certain seconds after causing an input signal (received by a terminal like a clock input terminal for example) to vary itself. Conventionally, the "setup time" and the "hold time" are collectively called "AC characteristic" of input terminals. Referring now to the timing chart shown in FIG. 2, a concrete example of the "AC characteristic" is described below.
Now, a consideration is given in regard to a case in which a semiconductor device executes a specific operation by applying an input signal SI at the falling edge of an input latch clock LCLK. The input signal SI goes HIGH at a moment T1-second earlier than the falling edge of the input latch clock LCLK, and then, after staying at HIGH level for a period corresponding to T1+T2 seconds, the input signal SI goes LOW. As shown in FIG. 2-d, the semiconductor device can execute the predetermined operation based on an input signal when the setup time of the input terminal is ST&lt;T1 and the hold time HT&lt;T2. On the other hand, as shown in FIG. 2-c, the setup time of the input terminal is ST&lt;T1. However, since the time T2 does not satisfy the hold time HT when the hold time HT is longer than the time T2 (HT&gt;T2), the semiconductor system does not execute the predetermined operation. As a result, as shown in FIG. 2-c, when feeding the input signal SI to the semiconductor device containing the relationship HT&gt;T2, it is essential for the semiconductor device to delay the input signal SI in order that the input signal SI can remain in the relationship HT&lt;T2. Accordingly, as shown in FIG. 2-c and -d, when feeding the identical input signal SI to a pair of semiconductor devices containing setup time and hold time, that is, different AC characteristics, it is essential for any conventional semiconductor device to delay the input signal that is to be delivered to such a semiconductor device containing a short setup time and a long hold time in order that the input signal can satisfy the AC characteristic.
The description above will be explained referring to the drawings.
FIG. 1 illustrates an example of the connection between a pair of conventional semiconductor devices having different AC characteristics while feeding input signal to these. FIG. 2 illustrates the timing chart. The reference numerals 2 and 3 respectively designate a pair of semiconductor devices containing the setup time and the hold time which are different from each other. As shown in FIG. 2-c, the value of the setup time ST of an input terminal 21 of a semiconductor device 2 is shorter than that of the other input terminal 31 of the other semiconductor device 3. Conversely, the value of the hold time of the input terminal 21 is longer than that of the other input terminal 31. Since the input terminal 21 has the hold time HT which is longer than the time T2, input signal SI is delivered to the input terminal 21 via a delay element 10. The delivered input signal SI is latched at the falling edge of input latch clock LCLK which has been given to the clock input terminals 22, 32. When latching the input signal SI which has been delivered to the input terminals 21 and 31 at the falling edge of the input latch clock LCLK, if the input signal SI is directly delivered to the input terminal 21 without being routed through the delay element 10, since time T1 (a period in which the input latch clock LCLK varies itself at the falling edge after the input signal SI goes HIGH) is longer than the setup time ST of the input terminal 21, no problem arises. Nevertheless, since time T2 (a period in which the input signal SI remains HIGH after causing the input latch clock LCLK to vary itself at the falling edge) is shorter than the predetermined hold time HT, the semiconductor device 2 cannot execute the prescribed operation. As a result, there is a need of delaying the input signal SI by operating the delay element 10 in order that the input signal SI can become compatible with the AC characteristic of the input terminal 21 to cause the time T2 (a period in which the input signal SI holds the value after the input latch clock LCLK varies) to satisfy the hold time HT.
On the other hand, proper value of delay time per output terminal of any conventional semiconductor device is prescribed. When feeding signal output from one of a pair of the connected semiconductor devices to the other semiconductor device synchronous with the input latch clock LCLK, since the input terminal of the other semiconductor device contains the AC characteristic shown in FIG. 2-c, when externally feeding the signal output from this semiconductor device on the basis of the timing shown in FIG. 2-b, this semiconductor device also needs to delay the output signal.
The Japanese Laid-Open Patent Publication No. 61-160128 of 1986 discloses an integrated circuit reflecting one of those prior arts intended for solving the above problem. The disclosed integrated circuit incorporates a delay circuit for determining the delay amount of internal clock pulse against external clock pulse in order to permit the connection between a plurality of semiconductor devices containing own setup time and hold time different from each other. FIG. 3 illustrates the schematic block diagram of the semiconductor device disclosed in the above publication. A delay circuit 11 is installed in a semiconductor device 2. The delay circuit 11 incorporates a plurality of delay elements 10 each being provided with a predetermined delay amount, a plurality of delay routes which connects these delay elements 10 in one or more than one series respectively receiving an external clock pulse EXCLK, and then, the delay circuit 11 causes the delay amount to vary itself by causing an internal-clock selecting circuit 5 to select the delay route by applying a control signal CTRL from an external source. In consequence, this prior art can connect these semiconductor devices containing different AC characteristics without necessarily providing delay elements outside of the semiconductor device. This semiconductor device can be offered to a variety of practical uses.
Nevertheless, since the delay circuit 11 contains a plurality of delay routes incorporating a plurality of delay elements 10, in order to prepare n-kinds of delay amount, the delay circuit 11 needs to prepare n-units of delay routes. This results in the expanded area of the delay circuit occupying the interior of the semiconductor device, thus causing the own size of the semiconductor device to be enlarged.